Title :
A hardware implementation of Multi-level Threshold Logic for Artificial Neural Net
Author_Institution :
Univ. of Manchester, Manchester
Abstract :
The need to implement neural structures is paramount, and a more device-centric view leads to an understanding of the scope of performance enhancements that can be achieved. A sequence of empirical investigations and their rationale are described, in which different types of simple junction-based devices perform multi-level threshold logic functions that are required for neural systems. This enables connectionists to comprehend the types of building blocks that can be used to implement connectionist systems. The paper focuses on early results: some of the aims have been demonstrated and amplified through empirical implementations, making it possible to assess the strength and weakness of the approach.
Keywords :
neural nets; threshold logic; artificial neural net; connectionist systems; hardware implementation; junction-based devices; multilevel threshold logic; Artificial neural networks; CMOS technology; Circuit testing; Environmental economics; Logic devices; Logic functions; Neural network hardware; Neural networks; Silicon; Stress; hardware implementation; multi-level; neural functionality; neural networks; threshold logic;
Conference_Titel :
Neural Networks, 2006. IJCNN '06. International Joint Conference on
Conference_Location :
Vancouver, BC
Print_ISBN :
0-7803-9490-9
DOI :
10.1109/IJCNN.2006.247213
