DocumentCode
2773261
Title
A delay-locked frequency synthesizer with low phase noise performance
Author
Du, Qingjin ; Zhuang, Jingcheng ; Kwasniewski, Tad
Author_Institution
Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
fYear
2003
fDate
16-18 Dec. 2003
Firstpage
461
Lastpage
464
Abstract
This paper presents a delay-locked frequency synthesizer implemented in 0.18 μm CMOS technology. Symmetrical structures were employed in the circuit to reduce the inter-period jitter and phase noise. With the reference signal from an RF generator, the measured phase noise performance is of -105.5 dBc/Hz at 10 kHz offset with the carrier frequency of 2.07 GHz.
Keywords
CMOS logic circuits; delay lines; delay lock loops; frequency synthesizers; integrated circuit design; integrated circuit modelling; integrated circuit noise; jitter; phase detectors; phase locked loops; phase noise; radiofrequency integrated circuits; 0.18 micron; 10 kHz; 2.07 GHz; CMOS technology; RF; RF generator; carrier frequency; delay-locked frequency synthesizer; inter-period jitter; phase noise; reference signal; CMOS technology; Circuits; Delay; Frequency measurement; Frequency synthesizers; Jitter; Phase noise; RF signals; Radio frequency; Signal generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices and Solid-State Circuits, 2003 IEEE Conference on
Print_ISBN
0-7803-7749-4
Type
conf
DOI
10.1109/EDSSC.2003.1283573
Filename
1283573
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