Evaluation of I-Cache Locking Technique for Real-Time Embedded Systems

Cache memory improves performance by reducing the speed gap between the CPU and the main memory. However, the execution time becomes unpredictable due to the cache´s adaptive and dynamic behavior. Real-time applications are subject to operational deadlines and predictability is considered necessary to support them. Studies show that for embedded systems, cache locking helps determine the worst case execution time (WCET) and cache-related preemption delay. In this work, we evaluate predictability of an embedded system running real-time applications by instruction cache (I-Cache) locking. We implement an algorithm that locks the blocks that may cause more cache misses, using the Heptane simulation tool. We obtain CPU utilization measures for both cache analysis (no cache locking) and I-cache locking. Experimental results show that our proposed cache locking algorithm improves predictability and performance up to 15% locking, after that, predictability may be further enhanced by sacrificing performance.