Switched capacitor architecture for prime length discrete Hartley transform

This paper describes an analog VLSI architecture, capable of computing discrete Hartley transform (DHT), and its inverse, for any prime N and its multiple of two and four, using standard analog blocks. The scheme operates from the general expression of DHT where the Input samples are multiplied by all the DHT coefficients, simultaneously using an array of capacitors. These multiplied values are then switched simultaneously with the help of cross point switch, to different integrators for performing necessary addition/subtraction. Here switched capacitor integrators are used to compute the transform, with capacitor ratios controlling the kernel coefficients. Proposed scheme shares maximum hardware when kernel coefficients pattern become regular. It is shown that for multiples of two and four, the same module used for primes can be reused and thus gives a modular architecture. It is suitable for real time applications with reasonable accuracy.