Modeling and mitigation techniques of the magnetic integrated structures parasitic capacitance

The magnetic planar technology is nowadays an attractive solution for designing the Electromagnetic Interference (EMI) filters due to its efficiency at high frequencies and its mechanical robustness. On the other hand, the general trend of reducing the dimensions of the integrated structures one inherently leads to the increase of their structural parasitic effects. Therefore, the minimization of the parasitic capacitances and inductances represents an important issue for increasing the performances of a magnetic integrated structure. In this light, the aim of this paper is to present the authors contribution to developed structural parasitic capacitance reduction solutions from devices realized in planar magnetic technology. Being structures with an important geometrical complexity, the structural parasitic capacitance cannot be defined by direct calculation expressions and it cannot be localized in one device, it being practically distributed in the space between the coil wirings that form the structure. So, in this paper, are proposed approached techniques to reduce the structural parasitic capacitance in planar magnetic integrated structures.