• DocumentCode
    2774454
  • Title

    A divide-and-conquer algorithm for 3D capacitance extraction [IC modeling]

  • Author

    Yu, Fangqing ; Shi, Weiping

  • Author_Institution
    Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
  • fYear
    2004
  • fDate
    2004
  • Firstpage
    253
  • Lastpage
    258
  • Abstract
    We present a new algorithm to improve the 3D boundary element method (BEM) for capacitance extraction. We partition large interconnect structures into small sections, set new boundary conditions using the border for each section, solve each section, and then combine the results to derive the capacitance. The target applications are critical nets, clock trees, or packages where 3D accuracy is required. Our algorithm is a significant improvement over the traditional BEMs and their enhancements, such as the "window" method where conductors far away are dropped, and the "shield" method where conductors hidden behind other conductors are dropped. Experimental results show that our algorithm is a magnitude faster than the traditional BEM and the window+shield method, for medium to large structures. The error of the capacitance computed by the new algorithm is within 2% for self capacitance and 7% for coupling capacitance, compared with the results obtained by solving the entire system using BEM. Furthermore, our algorithms gives accurate distributed RC, where none of the previous 3D BEM algorithms and their enhancements can.
  • Keywords
    boundary-elements methods; capacitance; circuit simulation; divide and conquer methods; integrated circuit interconnections; integrated circuit modelling; 3D boundary element method; 3D capacitance extraction; BEM; IC modeling; accurate RC distribution; clock trees; coupling capacitance; critical nets; divide-and-conquer algorithm; hidden conductor dropping; large interconnect structure partitioning; remote conductor dropping; self capacitance; shield method; window method; Approximation algorithms; Boundary element methods; Clocks; Conductors; Equations; Integrated circuit interconnections; Iterative algorithms; Linear systems; Parasitic capacitance; Partitioning algorithms;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Quality Electronic Design, 2004. Proceedings. 5th International Symposium on
  • Print_ISBN
    0-7695-2093-6
  • Type

    conf

  • DOI
    10.1109/ISQED.2004.1283682
  • Filename
    1283682