Title :
Optimizing cost and thermal performance: rapid prototyping of a high pin count cavity-up enhanced plastic ball grid array (EPBGA) package
Author_Institution :
Package Characterization Lab., ChipPAC Inc., Chandler, AZ, USA
Abstract :
A three-dimensional finite element model of a 420 lead (5 row perimeter) cavity-up enhanced plastic ball grid array (EPBGA) package was developed using the ANSYS/sup TM/ finite element simulation code. The developed model was utilized to perform a sensitivity analysis in order to quantify the effects of varying package and system motherboard designs. Design variables included: (1) chip size; (2) package substrate metallized plane layers; (3) motherboard metallized plane layers; (4) inner solder ball matrix and vias; (5) package aluminum heat spreader thickness; and (6) chip power dissipation. Predicted package junction-to-ambient thermal resistance (/spl theta//sub JA/) values were used in conjunction with a central composite design of experiments to develop a response surface equation which quickly predicts EPBGA package thermal performance as a function of the six design variables. The methodology described allows for rapid analysis of design options in the "dynamic" environment of prototyping, and the implementation of optimized cost effective package designs to meet required standards under multiple customer environments.
Keywords :
ball grid arrays; circuit CAD; circuit optimisation; design of experiments; finite element analysis; heat sinks; integrated circuit design; integrated circuit interconnections; integrated circuit packaging; plastic packaging; rapid prototyping (industrial); sensitivity analysis; soldering; thermal resistance; 3D finite element model; ANSYS finite element simulation code; EPBGA package thermal performance; cavity-up enhanced PBGA package; cavity-up enhanced plastic ball grid array package; central composite design of experiments; chip power dissipation; chip size; cost optimization; design variables; inner layer vias; inner solder ball matrix; motherboard metallized plane layers; multiple customer environments; optimized cost effective package design; package aluminum heat spreader thickness; package design; package junction-to-ambient thermal resistance; package substrate metallized plane layers; pin count; rapid design analysis; rapid prototyping; response surface equation; sensitivity analysis; system motherboard design; thermal performance optimization; Cost function; Electronics packaging; Finite element methods; Lead; Metallization; Plastic packaging; Prototypes; Sensitivity analysis; Surface resistance; Thermal resistance;
Conference_Titel :
Semiconductor Thermal Measurement and Management Symposium, 1999. Fifteenth Annual IEEE
Conference_Location :
San Diego, CA, USA
Print_ISBN :
0-7803-5264-5
DOI :
10.1109/STHERM.1999.762440