Estimating phase-locked loop jitter due to substrate coupling: a cyclostationary approach

On-chip phase-locked loops (PLLs) are critical components for clock generation and recovery in high-speed communication and data processing systems. The presence of partially-correlated substrate noise presents a new challenge to predicting PLL jitter. We propose a model that describes the substrate noise-to-jitter transfer characteristics for CMOS ring oscillator-based PLLs on epitaxial substrates. The proposed model is verified against jitter simulations.