SPICE-compatible thermal simulation with lumped circuit modeling for thermal reliability analysis based on modeling order reduction

With the growing power dissipation in modem high performance VLSI designs, nonuniform temperature distribution and limited heat-conduction capability have caused thermal induced performance and reliability degradation. However the problem modeled by finite difference method for interconnect reliability analysis has huge size if we require the resolution with wire width. In addition, the generated lumped circuit has significant number of input sources, and the bottleneck of traditional model reduction methods is the big number of input ports. In this paper we propose a method of SPICE-compatible thermal simulation for interconnect reliability analysis. The lumped thermal circuit modeling with adaptive approach is used to reduce the problem size. The improved extended Krylov subspace (IEKS) method, independent of the number of input ports, is used for thermal simulation. The experimental results show that our method provides highly accurate results with performance improvement 15 x over T-Spice for the problem with node number 72428.