Title :
Low power and high performance circuit techniques for high fan-in dynamic gates
Author :
Yang, Ge ; Wang, Zhongda ; Kang, Sung-Mo
Author_Institution :
Dept. of Electr. Eng., California Univ., Santa Cruz, CA, USA
Abstract :
Domino keeper has to be upsized to keep the noise margin in high fan-in dynamic gates, which increases the power consumption and slows down the evaluation. We propose a four-phase non-full swing keeper design to solve this dilemma. Non-full swing switching at the keeper gate together with alleviated contention help to reduce power consumption and delay. Simulation of 16-input OR gate using 0.13μm CMOS SPICE parameters shows that proposed keeper design can reduce power consumption and delay by 26% and 24%, respectively.
Keywords :
CMOS logic circuits; SPICE; VLSI; circuit simulation; integrated circuit design; logic CAD; logic gates; low-power electronics; power consumption; CMOS SPICE parameters; OR gate simulation; VLSI circuits; alleviated contention; conditional keeper; design tradeoffs; domino keeper; four-phase nonfull swing keeper; high fan-in dynamic gates; high performance circuit techniques; low power circuit techniques; power consumption; timing requirements; CMOS logic circuits; Circuit noise; Circuit simulation; Clocks; Delay; Energy consumption; Short circuit currents; Subthreshold current; Threshold voltage; Very large scale integration;
Conference_Titel :
Quality Electronic Design, 2004. Proceedings. 5th International Symposium on
Print_ISBN :
0-7695-2093-6
DOI :
10.1109/ISQED.2004.1283710
