DocumentCode
2775082
Title
Concurrent error detection for combinational and sequential logic via output compaction
Author
Almukhaizim, Sobeeh ; Drineas, Petros ; Makris, Yiorgos
Author_Institution
Dept. of Electr. Eng., Yale Univ., New Haven, CT, USA
fYear
2004
fDate
2004
Firstpage
459
Lastpage
464
Abstract
We discuss the problem of non-intrusive concurrent error detection (CED) for random logic. We analyze the optimal solution model and we point out the limitations that prevent logic synthesis from yielding a minimal cost implementation. We explain how duplication-based CED exploits decomposition to alleviate these limitations for the unrestricted error model. We then examine a compaction-based CED method, which employs a similar decomposition principle to alleviate synthesis limitations for restricted error models. We demonstrate the cost reduction achieved by the decomposed method through experimental results and we discuss the points where optimality is lost, possible remedies, and extension to finite state machines (FSMs).
Keywords
circuit optimisation; combinational circuits; finite state machines; logic design; logic testing; sequential circuits; FSM; combinational logic; decomposition method; duplication-based CED; finite state machines; logic synthesis; minimal cost implementation; nonintrusive concurrent error detection; output compaction; random logic CED; sequential logic; unrestricted error model; Circuit faults; Circuit testing; Compaction; Computer errors; Cost function; Delay; Electrical fault detection; Fault detection; Hardware; Logic;
fLanguage
English
Publisher
ieee
Conference_Titel
Quality Electronic Design, 2004. Proceedings. 5th International Symposium on
Print_ISBN
0-7695-2093-6
Type
conf
DOI
10.1109/ISQED.2004.1283716
Filename
1283716
Link To Document