FinFET SRAM - device and circuit design considerations

Author

Ananthan, Hari ; Bansal, Aditya ; Roy, Kaushik

Author_Institution

Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA

fYear

2004

fDate

2004

Firstpage

511

Lastpage

516

Abstract

The quasi-planar double-gate FinFET has emerged as one of the most likely successors to the classical planar MOSFET for ultimate scalability. Unlike planar devices, its channel width is in the vertical direction; hence it is possible to increase effective channel width (and hence drive current) per unit planar area by increasing fin-height (SOI thickness). This translates directly to improved performance in interconnect-dominated circuits. In this paper we explore the joint V_dd-fin-height-V_t design space for a 65 nm FinFET SRAM. We report that 69% taller fins can accommodate 18% (140 mV) lower V_dd as well as 35 % (70 mV) higher V_t to deliver iso-performance at 87% lower sub-threshold leakage, 50% lower gate leakage, 25% lower dynamic energy, 13% higher static noise margin and 38% higher critical charge for soft-error immunity.

Keywords

CMOS memory circuits; SRAM chips; integrated circuit design; leakage currents; silicon-on-insulator; 65 nm; SOI thickness; SRAM; critical charge; effective channel width; fin-height; gate leakage; interconnect-dominated circuits; quasi-planar double-gate FinFET; soft-error immunity; static noise margin; sub-threshold leakage; vertical channel width direction; Circuit synthesis; Delay; FinFETs; Gate leakage; Integrated circuit interconnections; MOSFET circuits; Microprocessors; Random access memory; Scalability; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Quality Electronic Design, 2004. Proceedings. 5th International Symposium on

Print_ISBN

0-7695-2093-6

Type

conf

DOI

10.1109/ISQED.2004.1283724

Filename

1283724