Title :
IEE Colloquium on `Processing Issues for VLSI/ASIC Designers´ (Digest No.152)
Abstract :
The following topics were dealt with: packages for gate arrays and standard cells; mixed analogue-digital ASIC processing issues; SOI for high-performance ASIC designs; fabrication technology for ASIC and VLSI designers; and scalable design rules vs. rule based compilation/compaction
Keywords :
VLSI; application specific integrated circuits; education; integrated circuit technology; packaging; ASIC designers; SOI; VLSI designers; fabrication technology; gate arrays; high-performance ASIC designs; mixed analogue-digital ASIC; monolithic IC; packages; rule based compaction; rule based compilation; scalable design rules; semicustom design; standard cells;
Conference_Titel :
Processing Issues for VLSI/ASIC Designers, IEE Colloquium on
Conference_Location :
London
