DocumentCode
277549
Title
Silicon-on-insulator for high performance ASIC designs
Author
Stern, John M. ; Ivey, Peter A. ; Davidson, Simon ; Walker, Simon N.
Author_Institution
Dept. of Electron. & Electr. Eng., Sheffield Univ., UK
fYear
1992
fDate
33777
Firstpage
42430
Lastpage
42434
Abstract
The authors describe the design of a 50000 gate data encryption processor in a 0.7 μm silicon-on-insulator (SOI) CMOS technology and compares it to the same processor implemented in a 0.7 μm bulk CMOS process. Silicon-on-insulator technology is described in detail and its inherent advantages and disadvantages are discussed. The performance advantages of SOI over conventional bulk technology results in a target clock speed of 150 MHz compared to 100 MHz. The authors also show that SOI designs are similar and can produce more compact cells
Keywords
CMOS integrated circuits; application specific integrated circuits; digital signal processing chips; integrated circuit technology; semiconductor-insulator boundaries; 0.7 micron; 150 MHz; SOI CMOS technology; data encryption processor; high performance ASIC designs;
fLanguage
English
Publisher
iet
Conference_Titel
Processing Issues for VLSI/ASIC Designers, IEE Colloquium on
Conference_Location
London
Type
conf
Filename
170102
Link To Document