A High-Yield Area-Power Efficient DWT Hardware for Implantable Neural Interface Applications

Temporal processing of neural recordings with high-density microelectrode arrays implanted in the cortex is highly desired to alleviate the data telemetry bottleneck. By exploiting the energy compactness capabilities of the discrete wavelet transform (DWT), our previous work has shown that it is a viable data compression tool that faithfully preserves the information in the neural data. This paper describes an area-power minimized hardware implementation of the multi-level, multi-channel DWT. Performance tradeoffs and key design decisions for implantable applications are analyzed. A 32-channel, 4-level version of the circuit has been custom designed in 0.18mum CMOS and occupies only 0.16mm², making it very suitable for high-yield intra-cortical neural interface applications.