• DocumentCode
    2776344
  • Title

    Evaluating coverage collection using the VEasy functional verification tool suite

  • Author

    Pagliarini, Samuel Nascimento ; Haacke, Paulo André ; Kastensmidt, Fernanda Lima

  • Author_Institution
    Programa de Pos-Grad. em Microeletronica, Univ. Fed. do Rio Grande do Sul (UFRGS), Porto Alegre, Brazil
  • fYear
    2011
  • fDate
    27-30 March 2011
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    This paper describes a performance evaluation of coverage collection on different simulators. It also describes how coverage is collected using VEasy, a tool suite developed specifically for aiding the process of Functional Verification. A Verilog module is used as an example of where each coverage metric applies. The block and toggle coverage collection algorithms used in VEasy are presented and explained in detail. Finally, the results show that the algorithms used in VEasy are capable of performing coverage collection with a lower simulation overhead when compared with commercial simulators.
  • Keywords
    formal verification; hardware description languages; software performance evaluation; VEasy functional verification tool suite; Verilog module; block coverage collection algorithm; coverage collection performance evaluation; toggle coverage collection algorithm; Adders; Analytical models; Arrays; Automation; Hardware design languages; Integrated circuit modeling; Measurement; Functional verification; coverage analysis; coverage collection; dynamic verification; simulation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Workshop (LATW), 2011 12th Latin American
  • Conference_Location
    Porto de Galinhas
  • Print_ISBN
    978-1-4577-1489-4
  • Type

    conf

  • DOI
    10.1109/LATW.2011.5985893
  • Filename
    5985893