• DocumentCode
    2776414
  • Title

    Synthesis of Pulsed-Coupled Neural Networks in FPGAs for Real-Time Image Segmentation

  • Author

    Vega-Pineda, Javier ; Chacón-Murguía, Mario I. ; Camarillo-Cisneros, Roberto

  • Author_Institution
    Chihuhaua Inst. of Technol., Chihuahua
  • fYear
    0
  • fDate
    0-0 0
  • Firstpage
    4051
  • Lastpage
    4055
  • Abstract
    This paper describes the implementation of a system based on Pulse Coupled Neural Networks (PCNNs) and Field Programmable Gate Arrays (FPGAs). The PCNN implemented is oriented to the industrial application of segmentation in sequences of images. The work went through several real physical stages of implementation and optimization to achieve the needed performance. The greatest performance achieved by the digital system was of 250M pixels per second, enough to process a sequence of images in real time. Details of these stages about the neuron implementation with different Altera´s FPGAs families are presented. Furthermore, the implementation is compared with previous implemented schemes based on floating point DSP microprocessor.
  • Keywords
    digital signal processing chips; field programmable gate arrays; image segmentation; neural nets; real-time systems; FPGA; digital system; field programmable gate arrays; floating point DSP microprocessor; image sequence; industrial application; neuron implementation; pulse coupled neural network; real-time image segmentation; Digital signal processing; Digital systems; Field programmable gate arrays; Image segmentation; Microprocessors; Network synthesis; Neural networks; Neurons; Pixel; Real time systems;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Neural Networks, 2006. IJCNN '06. International Joint Conference on
  • Conference_Location
    Vancouver, BC
  • Print_ISBN
    0-7803-9490-9
  • Type

    conf

  • DOI
    10.1109/IJCNN.2006.246929
  • Filename
    1716657