Thermal Resistance Analysis of a Multi-Stack Flip Chip 3-D Package

This paper evaluates the thermal performance of a newly developed multi-stack flip chip package using the finite element method. The effect of the major parameters, identified as the solder material, the solder joint pitch, the solder joint height and the pad diameter on the thermal performance of the package is studied. Based on the finite element results, a lumped model is developed which is capable to give quick and promising results of the junction temperatures of the package for different solder joint configuration.