Test power reduction via deterministic alignment of stimulus and response bits

Toggling of scan cells during the shift of consecutive complementary values reflects into excessive switching activity in the combinational logic under test unnecessarily. Elevated levels of power dissipation during test ensue as a result, endangering the reliability of the chip. The test power problem may be alleviated via a proper specification of don´t care bits to create transition-less runs of bit values. However, in order to reduce Test Data Volume (TDV), these don´t care bits are typically exploited to encode patterns through the on-chip decompressor. Furthermore, this approach would not address scan-out and/or capture power. In this paper, we propose a DfT-based approach for reducing test power in any scan architecture. The proposed on-chip mechanism enables the alignment of transition-wise costly stimulus/response bits in scan slices, absorbing these transitions and reducing power. The proposed solution is test set independent and reduces power without resorting to x-filling, enabling orthogonal x-filling techniques to be applied in conjunction. Experimental results justify the efficacy of the proposed method in attaining test power reductions.