Residual Stress Distribution in Stacked LSI Chips Mounted by Flip Chip Technology

Since mechanical stress affects both electronic functions and reliability of LSI chips, it has become strongly important to minimize the residual stress in LSI chips. This is because the residual stress increases significantly by changing the bonding structure between an LSI chip and a substrate from a wire-bonding structure (WB) to a flip-chip structure (FC). A finite element analysis, therefore, was performed to make clear the quantitative residual stress distribution in stacked chips mounted by flip chip technology using area-arrayed metallic bumps. The maximum value of the normal stress on a transistor formation surface of a chip shifts about -200 MPa by changing the assembly structure from WB to FC. A periodic distribution with amplitude of about 90 MPa also appears due to the periodic alignment of the metallic bumps. Such a change of the residual stress in an LSI chip causes a shift of electronic functions of semiconductor devices in a local area of the chip. The important structural factors that determine the distribution of the residual stress are found to be the thickness of a chip, the height of a bump, the width of a bump, the period of the bumps, and the thermal expansion coefficient of underfill material. The average residual stress in the stacked two chips varies depending on the distance from a bending neutral axis of the stacked structure, and the local residual stress also varies depending on the relative position of bumps in an upper connection layer and a bottom connection layer. Therefore, it is very important to optimize the thickness of a chip, the position (layout) of bumps, and other structural factors to minimize not only the average residual stress but also the amplitude of the periodic stress distribution. Finally, the estimated stress distribution was proved in detail by experiments using stress-sensing chips with 10-mum long gauges.