A new Built-In Current Sensor scheme to detect dynamic faults in Nano-Scale SRAMs

Technology scaling has made possible the integration of millions of transistors into a small area allowing the increase of memory´s density. In this scenario, new defects generated during the manufacturing process have become important and challenging concerns for Nano-Scale Static Random Memories´ (SRAMs´) testing. Thus, functional fault models, traditionally applied in SRAMs´ testing, have become insufficient to correctly reproduce the effects caused by these defects. In more detail, new memory technologies have introduced new defects that cause dynamic faults, a previously unknown type of fault. In parallel, the rapidly increasing need to store more information results in the fact that the memory elements occupy great part of the System-on-Chip (SoC) silicon area. Therefore, memories have become the main responsible for the overall SoC yield. In this context, we propose a new Built-In Current Sensor (BICS) scheme to detect dynamic faults associated to resistive-open defects in SRAMs. Experimental results obtained throughout electrical simulation demonstrate the BICS´s fault detection capability. Finally, we lay out the benefits and limitations of the BICS´s adoption and point out the direction of future works.