DocumentCode :
2777160
Title :
Impact of SEU configurations on a SRAM cell response at circuit level
Author :
Micolau, G. ; Aziza, H. ; Castellani-Coulié, K. ; Portal, J.-M.
Author_Institution :
IMT Technopole de Chateau, Univ. Aix-Marseille, Marseille, France
fYear :
2011
fDate :
27-30 March 2011
Firstpage :
1
Lastpage :
5
Abstract :
This work focuses on the SEU simulation in a 90nm SRAM cell, in order to provide basic metrics for reliability studies. To do that, a charge generation model is used to simulate the impact of an ionizing particle striking a sensitive node. The current collected at this particular node is extracted and injected at a circuit level. Thus, a correlation between the circuit electrical behavior and the critical charge is presented.
Keywords :
SRAM chips; integrated circuit reliability; SEU configuration; SRAM cell; charge generation model; circuit electrical behavior; circuit level; reliability; size 90 nm; Integrated circuit modeling; Noise; Random access memory; Reliability; SPICE; Single event upset; Transient analysis; DNM; Noise source currents; Reliability; SRAM; Single Event Upset;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Workshop (LATW), 2011 12th Latin American
Conference_Location :
Porto de Galinhas
Print_ISBN :
978-1-4577-1489-4
Type :
conf
DOI :
10.1109/LATW.2011.5985936
Filename :
5985936
Link To Document :
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