An efficient symbolic approach to time delay optimization of CMOS circuits

An approach to automatic generation of symbolic models relating a digital cell delay to CMOS transistor dimensions is proposed and used for deterministic and statistical delay optimization in combinational CMOS VLSI circuits. The models used provide about 5% accuracy with respect to the SPICE-3 circuit simulator, but are up to 5 to 6 orders of magnitude faster. A first order statistical device model is introduced. Examples of optimization of several VLSI circuits are shown, the largest being composed of about 1200 transistors, with 380 gate widths and 10 different active delay paths optimized in 308 CPU seconds. A generic optimization system, able to perform the relevant deterministic and statistical optimization tasks, is described