Frequency Domain Based Topology Optimization for DRR2-533 DRAM Interface in SFF Domain

This paper discusses signal integrity (SI) challenges in interfacing Intelreg 945 GMS graphics and memory controller hub (GMCH) with DDR2-533 memory (both SO-DIMM and on board memory for SFF (small form factor) designs. SFF designs are constrained by power and space. This paper outlines SI analysis through frequency domain (FD) methodology and correlates with time domain (TD) results. This paper could serve as a guideline with theoretical and implementation details for platform architects and designers. Also it provides the strategic planning and marketing people with an insight on the rising SI challenges faced in interface of high speed and high density memories in SFF designs.