DocumentCode :
2778268
Title :
DRAM memory electrical yield improvement by backgrinding induced backside damage
Author :
Kuo, Kwei-Kuan ; Emoto, Shunya ; Tabuchi, Tomotaka ; Igami, Yukiko
Author_Institution :
NXP Semicond., Kaohsiung
fYear :
2006
fDate :
11-14 Dec. 2006
Firstpage :
1
Lastpage :
6
Abstract :
This work investigates the electrical yield improvement by backgrinding process on DRAM backside with different wafer grinding technologies. The level of damage present in wafer backside subjected to different grinding technology is characterized. By comparing TEM analysis of strain layer and electrical testing result from samples that had undergone different backgrinding technologies, the most effective suitable processing conditions for the purpose of DRAM yield improvement were determined.
Keywords :
DRAM chips; grinding; integrated circuit yield; DRAM memory; TEM analysis; backgrinding induced backside damage; electrical testing; electrical yield improvement; wafer grinding; Abrasives; Capacitors; Crystallization; Electronics packaging; Gettering; Impurities; Production; Random access memory; Silicon; Wheels;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Materials and Packaging, 2006. EMAP 2006. International Conference on
Conference_Location :
Kowloon
Print_ISBN :
978-1-4244-0834-4
Electronic_ISBN :
978-1-4244-0834-4
Type :
conf
DOI :
10.1109/EMAP.2006.4430675
Filename :
4430675
Link To Document :
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