DocumentCode :
2778370
Title :
New 3D Stacked Technology System for PoP/SiP & Electric Components
Author :
Hirai, Yukihiro
Author_Institution :
Adv. Syst. Japan Inc., Tokyo
fYear :
2006
fDate :
11-14 Dec. 2006
Firstpage :
1
Lastpage :
6
Abstract :
The need for advanced high-performance systems in the rapidly booming digital consumer electronic market, (i.e.: cellular phones, digital cameras, etc) is ever spiraling upward. SiP (system in a chip) technology is a powerful means to achieving miniaturizing and manufacturing of such high-performance electronics equipment. Some of the advantages of SiP when used in such electronics equipment offers overall flexibility due to its small size, thin type, and high-speed transmission rates, combined with low-power consumption and low-cost allowing for the best all-around technology. There are several SiP methods available; SoP (system on package) is most notable to offer faster-time-to-market and it\´s ease of re-design as its greatest advantages. In particular, the PoP / SiP JISSO method called "Spiral Contacttrade" (micro contact technology) is a unique market created by Advanced Systems Japan (ASJ) which offers solutions in a 3D stacked system array. Features of 3D stacked technology system are: (1) Only KGD (known good die) will be accumulated, which in turn drops the bad yield problem to minimal numbers, and the restrictions when applied in the semiconductor and electronic parts sector are minimal. (2) It is also very flexible in allowing manufacturers the ability and ease to work with specification changes especially in memory capacity etc. because it allows individual chips to be layered (or stacked in 3D). (3) The consolidation of the passive components (resistors, capacitors, coil, etc.) is also possible. (4) By combining several chips into one package shortens the inter-chip wiring distance. (5) As a result, the influence of EMI (electro-magnetic interference) noise is reduced, increasing stability while simultaneously increasing high-speed operation. (6) In addition, the bus design of the wiring for the high-speed operation between the microcomputer and memory, etc. becomes unnecessary, simplifying both design and reducing manufacturing costs in the process. (- 7) As a result, time to market is drastically reduced. (8) And this makes it easier to create a total system solution proposal without worrying about expensive development costs.
Keywords :
cost reduction; electrical contacts; integrated circuit technology; system-in-package; time to market; 3D stacked technology system; PoP/SiP; advanced high-performance systems; electric components; high-performance electronics equipment; manufacturing costs reduction; micro contact technology; passive components consolidation; reduced electromagnetic interference noise; spiral contact; system in a chip technology; time to market; total system solution; Cellular phones; Consumer electronics; Costs; Digital cameras; Electronic equipment; Electronic equipment manufacture; Flexible manufacturing systems; Manufacturing processes; Packaging; Wiring;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Materials and Packaging, 2006. EMAP 2006. International Conference on
Conference_Location :
Kowloon
Print_ISBN :
978-1-4244-0834-4
Electronic_ISBN :
978-1-4244-0834-4
Type :
conf
DOI :
10.1109/EMAP.2006.4430680
Filename :
4430680
Link To Document :
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