Impact of Low-k Devices on Failure Mode of Flip Chip Tensile Pull Test

Author

Endut, Zulkarnain ; Ahmad, Ibrahim ; Swee, G.L.H. ; Sukemi, Norazham Mohd

Author_Institution

Univ. Kebangsaan Malaysia, Bangi

fYear

2006

fDate

11-14 Dec. 2006

Firstpage

1

Lastpage

5

Abstract

In this paper, the failure mode and solder bump strength for low-k flip chip devices were determined using die pull technique. The results show there is no significant difference between low-k and non low-k devices in terms of bumps strength for the amount of taffy in this device. However, there is different in failure mode which shows an increasing in VRO and SRO failure mode. Die pull test within a time and bake factor also help to minimize VRO and SRO failure mode. However, VRO and SRO failure mode were expected as an another impact of low-k materials on flip chip packaging.

Keywords

chip scale packaging; failure (mechanical); failure analysis; flip-chip devices; integrated circuit interconnections; integrated circuit testing; low-k dielectric thin films; solders; tensile testing; die pull technique; failure modes; flip chip packaging; flip chip tensile pull test; low-k flip chip devices; silicon rip out failure mode; solder bump strength; via rip out failure mode; Adhesives; Copper; Dielectric materials; Flip chip; Lead; Packaging; Silicon; Soldering; Testing; Thermal stresses;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Materials and Packaging, 2006. EMAP 2006. International Conference on

Conference_Location

Kowloon

Print_ISBN

978-1-4244-0834-4

Electronic_ISBN

978-1-4244-0834-4

Type

conf

DOI

10.1109/EMAP.2006.4430682

Filename

4430682