Title :
Use of a theorem prover for transformational synthesis
Author :
Koelmans, A.U. ; Burns, F.P. ; Kinniment, D.J.
Author_Institution :
Newcastle upon Tyne Univ., UK
Abstract :
This work is concerned with provable correct transformational high level synthesis. Transformational synthesis is the process of generating a hardware implementation from an initial behavioural description, by repeatedly applying transformations to the behavioural descriptions until a satisfactory implementation can be generated. It is essential to verify the correctness of the applied transformations if the final implementation is to conform to the initial specification. The authors have implemented a prototype interactive design tool that integrates the Boyer Moore theorem prover into the design process in such a way as to guarantee functional correctness at all times
Keywords :
VLSI; logic design; theorem proving; Boyer Moore theorem prover; correctness; hardware implementation; high level synthesis; interactive design tool; theorem prover; transformational synthesis;
Conference_Titel :
Formal and Semi-Formal Methods for Digital Systems Design, IEE Colloquium on
Conference_Location :
London