A hardware implementation solution for DC-OFDM-based UWB PHY

This paper presents a dual-carrier orthogonal frequency-division multiplexing (DC-OFDM) based ultrawideband (UWB) PHY (RF front-end plus baseband processor) which is compliant with C-WPAN UWB standard. The proposed UWB PHY supports data rates from 53.2 to 480 Mbps, and demonstrates a packet-error-rate (PER) of 8% under multi-path fading, including CM1, CM2, and CM4 channel modes, additive white Gaussian noise (AWGN), and up to 50 ppm carrier frequency offset (CFO) and sampling frequency offset (SFO). It consists of a radio-frequency (RF) transceiver operating in the frequency band group 2 (6204-8844MHz), a 6-bit folding and interpolating analog-to-digital convertors (ADC), a 8-bit current-steering digital-to-analog convertor (DAC) and a digital baseband processor. The front-end circuits have been fabricated using 0.13μm CMOS Technology. The digital baseband processor has been implemented on a Xilinx Vertex-5 FPGA platform.