A multithreading architecture for low power processors

In this paper a multithreading architecture is proposed as a solution for the computing that has to be done using very limited power resources. The proposed structure supports four threads, all threads being available for the user computation. Using a multithreading architecture the power consumption is decreased considerably by removing the resources for speculation and ILP extraction. Reducing the die area as much as possible the cell´s internal power is reduced. Increasing the degree of utilization of the available hardware resources the net´s switching power is considerably reduced. We will show how a multithreading architecture can achieve these two goals without any decreasing in computing performance