MOSFET conductance modelling including distortion analysis aspects

The nanotechnology trend needs more precisely models for active devices. From this point of view the design of linear analog circuits lacks models for state-of-the-art MOS transistors to accurately describe the conductance and distortion effects. This is mainly due to inaccurate modelling of the second order effects induced by high vertical gate field such as mobility degradation and short channel series resistance and second order effects induced by parallel drain field like velocity saturation in the ohmic region and channel length modulation in the saturation region. After a rigorous description of transistor conductance in ohmic and saturation region we included these effects in the MOS transistor model, using a compact expression of drain current for computation reasons. The simulations using the new drain current expression were in good agreement with experimental data