• DocumentCode
    2779757
  • Title

    Architecture approaching the atomic scale

  • Author

    DeHon, André

  • Author_Institution
    Univ. of Pennsylvania, Philadelphia
  • fYear
    2007
  • fDate
    11-13 Sept. 2007
  • Firstpage
    11
  • Lastpage
    20
  • Abstract
    Both bottom-up and top-down techniques have been used to fabricate assemblies of devices and interconnect where key, density-defining feature sizes are on the order of ten atoms wide. We show how complete computing architectures can be constructed from these new techniques and building blocks despite high defect rates, extreme regularity requirements, and statistical assembly. We further highlight the paradigm shifts in integrated circuit design and architecture which appear necessary to accommodate these atomic-scale effects. Our estimates suggest a 10 nm full-pitch FPGA-like design can achieve one to two orders of magnitude greater logic density than ideal, defect-free lithographic scaling to 22 nm.
  • Keywords
    integrated circuit design; lithography; statistical analysis; atomic scale; bottom up techniques; defect free lithographic scaling; integrated circuit design; paradigm shifts; size 10 nm; size 22 nm; statistical assembly; top down techniques; Assembly; Atomic layer deposition; Atomic measurements; Computer architecture; Conducting materials; Dielectrics and electrical insulation; Nanowires; Semiconductivity; Semiconductor materials; Wires;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid State Device Research Conference, 2007. ESSDERC 2007. 37th European
  • Conference_Location
    Munich
  • ISSN
    1930-8876
  • Print_ISBN
    978-1-4244-1123-8
  • Electronic_ISBN
    1930-8876
  • Type

    conf

  • DOI
    10.1109/ESSDERC.2007.4430874
  • Filename
    4430874