An optimization method for placement of decoupling capacitors on printed circuit board

Author

Kamo, Atsushi ; Watanabe, Takayuki ; Asai, Hideki

Author_Institution

Dept. of Syst. Eng., Shizuoka Univ., Hamamatsu, Japan

fYear

2000

fDate

2000

Firstpage

73

Lastpage

76

Abstract

This paper investigates the optimal placement of decoupling capacitors on printed circuit boards (PCB). This method minimizes the impedance characteristics at the power supply in the specified frequency range in order to find the optimal decoupling capacitor position. In this method, the PCB is modeled via the partial element equivalent circuit (PEEC) model approach to handle the 3D structures, and the Krylov-subspace technique is used to obtain the impedance characteristics in the frequency domain efficiently

Keywords

capacitors; circuit optimisation; electric impedance; electromagnetic compatibility; electromagnetic interference; equivalent circuits; frequency-domain analysis; printed circuit design; 3D structures; Krylov-subspace technique; PCB; PEEC model; decoupling capacitor placement; decoupling capacitors; frequency domain impedance characteristics; impedance characteristics; optimal decoupling capacitor position; optimal placement; optimization method; partial element equivalent circuit model; power supply; printed circuit board; specified frequency range; Capacitance; Capacitors; Circuit simulation; Coupling circuits; Finite difference methods; Frequency; Impedance; Optimization methods; Power supplies; Printed circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Performance of Electronic Packaging, 2000, IEEE Conference on.

Conference_Location

Scottsdale, AZ

Print_ISBN

0-7803-6450-3

Type

conf

DOI

10.1109/EPEP.2000.895496

Filename

895496