Low-voltage limitations of memory-rich nano-scale CMOS LSIs

Author

Itoh, Kiyoo ; Horiguchi, Masashi ; Yamaoka, Masanao

Author_Institution

Hitachi Ltd., Tokyo

fYear

2007

fDate

11-13 Sept. 2007

Firstpage

68

Lastpage

75

Abstract

The low-voltage limitations of memory-rich nano-scale CMOS LSIs using bulk CMOS and fully-depleted (FD) SOI devices are described, focusing on CMOS inverter and flip-flop circuits such as six-transistor (6-T) cells in SRAMs and sense amplifiers in DRAMs. The limitations strongly depend on the ever-larger V_T variation, especially in SRAM cells and logic gates, and are improved by using the FD-SOI as well as by using repair techniques. Consequently, two possible LSIs are predicted to coexist in the deep-sub-100-nm generation: high-V_DD bulk CMOS LSIs for low-cost low-standby-current applications and low-V_DD FD-SOI LSIs for low-power applications.

Keywords

CMOS integrated circuits; CMOS memory circuits; DRAM chips; SRAM chips; large scale integration; logic gates; low-power electronics; nanoelectronics; silicon-on-insulator; CMOS inverter; DRAM; SRAM; bulk CMOS; flip-flop circuits; fully-depleted SOI devices; logic gates; low-voltage limitations; memory-rich nano-scale CMOS LSI; repair techniques; sense amplifiers; six-transistor cells; size 100 nm; CMOS logic circuits; CMOS memory circuits; CMOS technology; Flip-flops; Inverters; Laboratories; Logic devices; Nanoscale devices; Random access memory; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid State Device Research Conference, 2007. ESSDERC 2007. 37th European

Conference_Location

Munich

ISSN

1930-8876

Print_ISBN

978-1-4244-1123-8

Electronic_ISBN

1930-8876

Type

conf

DOI

10.1109/ESSDERC.2007.4430883

Filename

4430883