Multi-gate devices for the 32nm technology node and beyond

Author

Collaert, N. ; De Keersgieter, A. ; Dixit, A. ; Ferain, I. ; Lai, L.-S. ; Lenoble, D. ; Mercha, A. ; Nackaerts, A. ; Pawlak, B.J. ; Rooyackers, R. ; Schulz, T. ; San, K.T. ; Son, N.J. ; Van Dal, M.J.H. ; Verheyen, P. ; von Arnim, K. ; Witters, L. ; De Mey

Author_Institution

IMEC, Heverlee

fYear

2007

fDate

11-13 Sept. 2007

Firstpage

143

Lastpage

146

Abstract

Due to the limited control of the short channel effects, the high junction leakage caused by band-to-band tunneling and the dramatically increased V_T statistical fluctuations, the scaling of planar bulk MOSFETs becomes more and more problematic with every technology node. The ITRS roadmap predicts that from the 32 nm technology node on planar bulk devices will not be able to meet the stringent leakage requirements anymore and that multi-gate devices will be required. In this paper, the suitability of FinFET based multi-gate devices for the 32 nm technology and beyond will be discussed. Apart from the benefits, some technological challenges will be addressed.

Keywords

MOSFET; tunnelling; FinFET; ITRS roadmap; band-to-band tunneling; high junction leakage; multigate devices; planar bulk MOSFET; short channel effects; size 32 nm; stringent leakage; Centralized control; Circuits; FinFETs; Fluctuations; Instruments; Large scale integration; Leakage current; Lithography; MOSFETs; Tunneling;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid State Device Research Conference, 2007. ESSDERC 2007. 37th European

Conference_Location

Munich

ISSN

1930-8876

Print_ISBN

978-1-4244-1123-8

Electronic_ISBN

1930-8876

Type

conf

DOI

10.1109/ESSDERC.2007.4430899

Filename

4430899