Impact of the gate stack on the electrical performances of 3D multi-channel MOSFET (MCFET) on SOI

Author

Bernard, E. ; Ernst, T. ; Guillaumot, B. ; Vulliet, N. ; Garros, X. ; Maffini-Alvaro, V. ; Andrieu, F. ; Barral, V. ; Allain, F. ; Toffoli, A. ; Vidal, V. ; Delaye, V. ; Vizioz, C. ; Campidelli, Y. ; Kermarrec, O. ; Hartmann, J.-M. ; Borel, S. ; Faynot, O

Author_Institution

Minatec, Grenoble

fYear

2007

fDate

11-13 Sept. 2007

Firstpage

147

Lastpage

150

Abstract

For the first time, we integrated and compared the electrical performances of high-K / metal embedded gate in 3D multi-channel CMOSFETs (MCFETs) on SOI. The electrical characteristics of embedded gates obtained by filling cavities with TiN/HfO₂, TiN/SiO₂ or N+ poly-Si/SiO₂ were compared to a planar reference. In particular we investigated electron and hole mobility behaviours (300 K down to 20 K) in embedded and planar structures, the gate leakage current and the negative bias temperature instability (NBTI). Despite a lower mobility, TiN / Hf02 gate stack demonstrates the best I_ON/I_OFF compromise and exhibits NBTI life time higher than 10 years up to 1.3 V.

Keywords

MOSFET; hole mobility; leakage currents; silicon-on-insulator; 3D multichannel MOSFET; SOI; electrical characteristics; electrical performances; electron behaviours; embedded gates; embedded planar structures; gate leakage current; gate stack; hole mobility behaviours; negative bias temperature instability; CMOSFETs; Electric variables; Filling; Hafnium oxide; High K dielectric materials; High-K gate dielectrics; MOSFET circuits; Niobium compounds; Tin; Titanium compounds;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid State Device Research Conference, 2007. ESSDERC 2007. 37th European

Conference_Location

Munich

ISSN

1930-8876

Print_ISBN

978-1-4244-1123-8

Electronic_ISBN

1930-8876

Type

conf

DOI

10.1109/ESSDERC.2007.4430900

Filename

4430900