Title :
Design and characterization of STI compatible high-voltage NMOS and PMOS devices in standard CMOS process
Author :
Han, Xiaoliang ; Xu, Chihao
Author_Institution :
Saarland Univ., Saarbrucken
Abstract :
This paper presents the design of High-Voltage NMOS and PMOS devices with STI (shallow trench isolation) technology fully compatible with a standard 0.25 mum/5 V CMOS process technology. Breakdown voltages of 35 V for n-channel with a specific on resistance of 1.96 mOmega.cm2 and -45 V for p-channel with a specific on-resistance of 8.73 mOmega.cm2 have been achieved without any modification of existing standard CMOS process.
Keywords :
CMOS integrated circuits; isolation technology; STI compatible device; high-voltage NMOS device; high-voltage PMOS devices; shallow trench isolation; standard CMOS process; voltage -45 V; voltage 35 V; CMOS logic circuits; CMOS process; CMOS technology; Isolation technology; Logic design; Logic devices; Low voltage; MOS devices; Silicon; Transistors;
Conference_Titel :
Solid State Device Research Conference, 2007. ESSDERC 2007. 37th European
Conference_Location :
Munich
Print_ISBN :
978-1-4244-1123-8
Electronic_ISBN :
1930-8876
DOI :
10.1109/ESSDERC.2007.4430907
