Interconnect characterization and design optimization for high speed digital applications

Interconnect plays a key role in determining the performance of high speed digital systems such as the direct Rambus^(R) DRAM (RDRAM^(R)) channel, which supports an 800 Mbit/s transfer rate with a 200 ps signal edge transition time. Design challenges are to achieve reliable high speed operations using low cost interconnect and conventional printed circuit board technologies. Impedance discontinuities and crosstalk due to interconnects must be minimized. Design optimization techniques must be employed to achieve desired system performance and robustness. This paper describes a set of experiments used to quantify the effects of various interconnect structures commonly found in printed circuit board design. Techniques for optimizing the performance of these interconnects are investigated