Globally asynchronous locally synchronous micropipelined processor implementation in FPGA

Author

Zafar, Y. ; Ahmad, M.M.

Author_Institution

Dept. of Electron. Eng., Mohammad Ali Jinnah Univ., Islamad

fYear

2005

fDate

18-18 Sept. 2005

Firstpage

277

Lastpage

282

Abstract

This paper deals with the implementation of globally asynchronous locally synchronous (GALS), micropipelined processor in field programmable gate arrays (FPGA). Associated issues like delay model incorporating on-chip, technology independent single inverter ring oscillator (SIRO) and an unbundled datapath based on bit-encoding and return-to-zero (RTZ) schemes are also presented. Post-layout simulation results are presented to describe the behavior of various sections of the design

Keywords

field programmable gate arrays; invertors; microprocessor chips; oscillators; pipeline processing; FPGA; bit-encoding; field programmable gate arrays; globally asynchronous local synchronous micropipelined processor; return-to-zero schemes; single inverter ring oscillator; Circuits; Clocks; Field programmable gate arrays; Inverters; Leg; Logic devices; Logic programming; Propagation delay; Reconfigurable logic; Ring oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Emerging Technologies, 2005. Proceedings of the IEEE Symposium on

Conference_Location

Islamabad

Print_ISBN

0-7803-9247-7

Type

conf

DOI

10.1109/ICET.2005.1558894

Filename

1558894

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2780535