Data acquisition and handling for the simulation of ASIC by utilizing SW/HW co-design methodology

ASIC design in the area of image processing needs large input output pixel data to be dealt with. The input image data is generated from input image which creates problems during ASIC simulation process. Manual manipulation of such a large data is not feasible while developing test bench for ASIC testing and simulation. This paper presents the methodology to highlight the approach of co-design to be used in such applications. Moreover, a revised scalable compression algorithm is proposed based on discrete cosine transform to improve ASIC behavioral architecture.