A novel scheme for irregular parallel-prefix adders

A schematic of a new 64-bit adder is presented in this paper. This adder uses the Manchester Carry Chain carry lookahead modules with spans of 4, 3, and 2. Only the first level has intermediate outputs. Unlike carry-ripple adders at the output of the Spanning Tree Carry Lookahead Adder (SPT) and the Recursive Carry-Lookahead/Carry-Select Hybrid Adder (RCS), the proposed irregular Parallel-Prefix (IPP) adder provided parallel addition at the output thus significantly reducing the number of transistors with a promising compatible speed. This will cause a considerable improvement in cost-performance. Without a carry-skip circuit, this adder also works well with a carry-in of “1” based on Brent-Kung (1982) and Tyagi´s (1993) lemmas. Because the IPP adder is unidirectional, it is more appropriate for pipeline implementation. Preliminary simulation results by Mentor Graphics at static gate-level have indicated that IPP adders are faster than Tyagi´s 16-bit, 32-bit and 64-bit Select-Prefix Adders. SPICE simulation at a transistor-level for a 16-bit IPP adder shows a speed of 1.756 ns. It reduces the transistor-count approximately by 21% compared to the RCS adder and by 18% compared to the SPT adder