Title :
Power optimized logic circuit design with a novel synthesis technique
Author :
Balasubramanian, P. ; Narayana, M. R Lakshmi ; Chinnadurai, R.
Abstract :
The purpose of this paper is to propose a systematic methodology for non-regenerative, logic circuit design at the gate level. The. traditional logic synthesis methods [Karnaugh, M 1953], [McCluskey EJ, 1956] become ineffective in case of non-adjacent functions, in this paper, we address the. reduction problem for this case by evolving a set of minimization lemmas based on the Hamming distance between the terms. Though our main emphasis has been on the satisfiability of the circuit functionality with minimum number of active gates, the approach presented here takes a viewpoint, in which all critical design metrics are investigated with the primary goal of reducing the dynamic power consumption of the circuit. The SPICE simulation results obtained on the basis of 3.3 V, 0.5 μm CMOS technology are very encouraging, as they report minimization in average power consumption by about 36 % for the examples cited, along with a substantial improvement in the figure of merit (FoM) of the circuit, in comparison with that obtainable using conventional approaches.
Keywords :
CMOS digital integrated circuits; active networks; logic circuits; logic design; logic gates; network synthesis; 3.3 V; CMOS technology; Hamming distance; SPICE simulation; active gates; circuit functionality; dynamic power consumption; figure of merit; logic circuit design; logic synthesis methods; nonadjacent functions; nonregenerative design; power optimized logic circuit design; synthesis technique; CMOS logic circuits; CMOS technology; Circuit synthesis; Design optimization; Energy consumption; Hamming distance; Logic circuits; Logic design; Minimization; Very large scale integration;
Conference_Titel :
Emerging Technologies, 2005. Proceedings of the IEEE Symposium on
Print_ISBN :
0-7803-9247-7
DOI :
10.1109/ICET.2005.1558899
