Author :
Aimé, D. ; Fenouillet-Beranger, C. ; Perreau, P. ; Denorme, S. ; Coignus, J. ; Cros, A. ; Fleury, D. ; Faynot, O. ; Vandooren, A. ; Gassilloud, R. ; Martin, F. ; Barnola, S. ; Salvetat, T. ; Chabanne, G. ; Brevard, L. ; Aminpur, M. ; Leverd, F. ; Gwozieck
Abstract :
This paper describes the fabrication and electrical behavior of a fully-depleted SOI technology using a direct metal gate and high-k dielectric integrated on 300 mm SOI wafers for low power applications. We report ultra-thin FDSOI MOS transistors with WN metal gate (capped with TiN) on HfSiON gate dielectric. Performance at both device and circuit level are demonstrated and compared with TiN midgap metal gate.
Keywords :
CMOS integrated circuits; MOSFET; low-power electronics; silicon-on-insulator; SOI wafers; WN metal gate; WxN metal gate; direct metal gate; electrical behavior; fully-depleted SOI CMOS technology; high-k dielectric; low power application; ultra-thin FDSOI MOS transistors; Annealing; CMOS technology; Fabrication; High-K gate dielectrics; MOCVD; MOSFETs; Paper technology; Semiconductor films; Threshold voltage; Tin;
