Fully-depleted SOI CMOS technology using WXN metal gate and HfSixOyNZ high-k dielectric

Author

Aimé, D. ; Fenouillet-Beranger, C. ; Perreau, P. ; Denorme, S. ; Coignus, J. ; Cros, A. ; Fleury, D. ; Faynot, O. ; Vandooren, A. ; Gassilloud, R. ; Martin, F. ; Barnola, S. ; Salvetat, T. ; Chabanne, G. ; Brevard, L. ; Aminpur, M. ; Leverd, F. ; Gwozieck

Author_Institution

Freescale Semicond., Crolles

fYear

2007

fDate

11-13 Sept. 2007

Firstpage

255

Lastpage

258

Abstract

This paper describes the fabrication and electrical behavior of a fully-depleted SOI technology using a direct metal gate and high-k dielectric integrated on 300 mm SOI wafers for low power applications. We report ultra-thin FDSOI MOS transistors with WN metal gate (capped with TiN) on HfSiON gate dielectric. Performance at both device and circuit level are demonstrated and compared with TiN midgap metal gate.

Keywords

CMOS integrated circuits; MOSFET; low-power electronics; silicon-on-insulator; SOI wafers; WN metal gate; WxN metal gate; direct metal gate; electrical behavior; fully-depleted SOI CMOS technology; high-k dielectric; low power application; ultra-thin FDSOI MOS transistors; Annealing; CMOS technology; Fabrication; High-K gate dielectrics; MOCVD; MOSFETs; Paper technology; Semiconductor films; Threshold voltage; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid State Device Research Conference, 2007. ESSDERC 2007. 37th European

Conference_Location

Munich

ISSN

1930-8876

Print_ISBN

978-1-4244-1123-8

Electronic_ISBN

1930-8876

Type

conf

DOI

10.1109/ESSDERC.2007.4430926

Filename

4430926