Fast modeling of core switching noise on distributed LRC power grid in ULSI circuits

Author

Zheng, L.-R. ; Tenhunen, H.

Author_Institution

Dept. of Electron., R. Inst. of Technol., Stockholm, Sweden

fYear

2000

fDate

2000

Firstpage

307

Lastpage

310

Abstract

A sophisticated on-chip power grid model consisting of distributed LRC elements is proposed for on-chip power distribution analysis. Fast equations for peak noise estimations are formulated. Noise distribution on a power grid with any topology is efficiently and accurately computed. HSPICE simulations confirmed its efficiency and accuracy. The model is suitable for both early stage analysis and post-layout verifications in on-chip power distribution design. Global and local optimization such as buffer sizing, power bus sizing, and on-chip decoupling capacitor placement can be easily conducted

Keywords

RC circuits; SPICE; ULSI; capacitors; circuit optimisation; circuit simulation; integrated circuit design; integrated circuit layout; integrated circuit noise; network topology; power supply circuits; HSPICE simulations; ULSI circuits; buffer sizing; core switching noise; distributed LRC elements; distributed LRC power grid; early stage analysis; global optimization; local optimization; model accuracy; model efficiency; modeling; noise distribution; on-chip decoupling capacitor placement; on-chip power distribution analysis; on-chip power distribution design; on-chip power grid model; peak noise estimation equations; post-layout verification; power bus sizing; power grid topology; Circuit noise; Inductance; Logic; Network-on-a-chip; Packaging; Power distribution; Power grids; Power system modeling; Switching circuits; Ultra large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Performance of Electronic Packaging, 2000, IEEE Conference on.

Conference_Location

Scottsdale, AZ

Print_ISBN

0-7803-6450-3

Type

conf

DOI

10.1109/EPEP.2000.895551

Filename

895551