Title :
Impact of interconnects on the optimal power-performance tradeoff for clock distribution in microprocessors
Author :
Saint-Laurent, Martin ; Swaminathan, Madhavan
Author_Institution :
Intel Corp., Austin, TX, USA
Abstract :
This paper discusses the tradeoff between power and clock inaccuracy for high-frequency microprocessors. A new expression for the optimal tradeoff is used to analyze the impact of interconnects on the optimal design point for a simple clock distribution network. The result is that the impact is considerable and that the cost of deviating from the optimal structure is substantial
Keywords :
circuit optimisation; clocks; integrated circuit design; integrated circuit interconnections; microprocessor chips; clock distribution; clock distribution network; high-frequency microprocessors; interconnects; microprocessors; optimal design point; optimal power-performance tradeoff; optimal structure; power-clock inaccuracy tradeoff; Capacitance; Clocks; Cost function; Frequency; Intelligent networks; Microprocessors; Performance analysis; Power dissipation; Topology; Voltage;
Conference_Titel :
Electrical Performance of Electronic Packaging, 2000, IEEE Conference on.
Conference_Location :
Scottsdale, AZ
Print_ISBN :
0-7803-6450-3
DOI :
10.1109/EPEP.2000.895552
