Title :
A high speed, low power spread spectrum code generator
Author :
Lowy, Menahem ; Anne, Krishna
Author_Institution :
Texas Univ., Arlington, TX, USA
Abstract :
This paper describes a parallel architecture implementation of a Gold code generator for a spread-spectrum communication system and its associated switch minimization algorithm. The parallel architecture dissipates less power than the conventional architecture based on serial linear feedback shift registers (LFSR) and also allows a higher throughput rate compared to the serial one where only one bit is generated per clock cycle. The Gold code generator implemented in a 2 micron CMOS technology consumes less than 1000 microwatts when clocked at 50 MHz
Keywords :
CMOS digital integrated circuits; parallel architectures; sequential codes; shift registers; spread spectrum communication; 1000 muW; 2 micron; 50 MHz; Gold code generator; clock cycle; parallel architecture implementation; spread spectrum code generator; switch minimization algorithm; throughput rate; CMOS technology; Clocks; Communication switching; Gold; Linear feedback shift registers; Minimization methods; Parallel architectures; Power generation; Spread spectrum communication; Switches;
Conference_Titel :
Circuits and Systems, 1994., Proceedings of the 37th Midwest Symposium on
Conference_Location :
Lafayette, LA
Print_ISBN :
0-7803-2428-5
DOI :
10.1109/MWSCAS.1994.519182
