Title :
Lateral-Extended (LatEx.) active for improvement of data retention time for sub 60nm DRAM era
Author :
Lee, Sungsam ; Park, Jongchul ; Lee, Kwangwoo ; Jang, Sungho ; Lee, Junho ; Byun, Hyunsook ; Kim, Ilgweon ; Choi, Yongjin ; Shim, Myoungseob ; Song, Duheon ; Park, Joosung ; Lee, Taewoo ; Shin, Dongho ; Jin, Gyoyoung ; Kim, Kinam
Author_Institution :
Samsung Electron. Co., Hwasung
Abstract :
A new active isolation structure, LatEx (lateral-extended) active, which exploits recess channel transistors, is proposed. By realizing the LatEx active, data retention time enhancement was successfully achieved in 60 nm technology node DRAM by virtue of reduced source/drain area and improved subthreshold slope due to decreased cross-sectional area of top trench profile and vertical bottom trench process. In this paper, LatEx active coupled with SRCAT is proved to be suitable for sub 60 nm DRAM cell array transistor technology.
Keywords :
DRAM chips; integrated circuit design; isolation technology; DRAM; SRCAT; cell array transistor technology; data retention time; lateral-extended active process; recess channel transistors; size 60 nm; trench profile; Computer aided engineering; Doping; Etching; Isolation technology; Project management; Random access memory; Scanning electron microscopy; Size control; Technological innovation; Transistors;
Conference_Titel :
Solid State Device Research Conference, 2007. ESSDERC 2007. 37th European
Conference_Location :
Munich
Print_ISBN :
978-1-4244-1123-8
Electronic_ISBN :
1930-8876
DOI :
10.1109/ESSDERC.2007.4430944
