Title :
On threshold circuits for parity
Author :
Paturi, Ramamohan ; Saks, Michael E.
Author_Institution :
Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
Abstract :
Motivated by, the problem of understanding the limitations of neural networks for representing Boolean functions, the authors consider size-depth tradeoffs for threshold circuits that compute the parity function. They give an almost optimal lower bound on the number of edges of any depth-2 threshold circuit that computes the parity function with polynomially bounded weights. The main technique used in the proof, which is based on the theory of rational approximation, appears to be a potentially useful technique for the analysis of such networks. It is conjectured that there are no linear size, bounded-depth threshold circuits for computing parity
Keywords :
neural nets; threshold logic; Boolean functions; almost optimal lower bound; neural networks; parity; polynomially bounded weights; rational approximation; size-depth tradeoffs; threshold circuits; Approximation methods; Boolean functions; Circuits; Computer architecture; Computer networks; Computer science; Convergence; Neural networks; Polynomials; Prototypes;
Conference_Titel :
Foundations of Computer Science, 1990. Proceedings., 31st Annual Symposium on
Conference_Location :
St. Louis, MO
Print_ISBN :
0-8186-2082-X
DOI :
10.1109/FSCS.1990.89559