On Automatic Test Block Generation for Peripheral Testing in SoCs via Dynamic FSMs Extraction

Traditional test generation methodologies for peripheral cores resort heavily to low-level descriptions of the circuit, leading to long generation times. Methodologies based on high-level descriptions can only be used if a clear relationship exists between the measured high-level coverage and the gate-level fault coverage. Even in medium complexity circuits, however, a direct relationship between code coverage metrics and fault coverage is not guaranteed, while other RT level metrics require an effort comparable to the use of low level descriptions. To overcome this problem, in the case of peripheral cores, a new approach is proposed: FSMs embedded in the system are identified and dynamically extracted via simulation, while transition coverage is used as a measure of how much the system is exercised. Model extraction and coverage maximization are performed concurrently in a completely automated way. This new technique is exploited to drive an unsupervised methodology for generating tests for peripheral cores. Experimental analysis shows the effectiveness of the approach.