A CLP-Based Functional ATPG for Extended FSMs

Author

Fummi, Franco ; Marconcini, Cristina ; Pravadelli, Graziano ; Harris, Ian G.

Author_Institution

Dept. of Comput. Sci., Univ. of Verona, Verona

fYear

2007

fDate

5-6 Dec. 2007

Firstpage

98

Lastpage

105

Abstract

It is a common opinion that semi-formal verification offers a good compromise between speed and exhaustiveness. In this context, the paper presents a semi-formal functional ATPG that joins static and dynamic techniques to generate high-quality test sequences. The ATPG works on a set of concurrent extended finite state machines (EFSMs) that models the design under verification (DUV). The test generation procedure relies on backjumping, for traversing the EFSM transitions, and constraint logic programming (CLP), for covering corner cases through the deterministic propagation of functional faults observed, but not detected, during the transition traversal.

Keywords

automatic test pattern generation; constraint handling; finite state machines; formal verification; logic programming; CLP-based functional ATPG; constraint logic programming; design under vetest generation procedurerification; extended FSM; extended finite state machines; high-quality test sequences; semiformal verification; static-dynamic techniques; transition traversal; Automatic test pattern generation; Computer science; Engines; Explosions; Fault detection; Hardware design languages; Logic programming; Logic testing; State-space methods; Test pattern generators; ATPG; CLP; EFSM; Functional verification;

fLanguage

English

Publisher

ieee

Conference_Titel

Microprocessor Test and Verification, 2007. MTV '07. Eighth International Workshop on

Conference_Location

Austin, TX

ISSN

1550-4093

Print_ISBN

978-0-7695-3241-7

Type

conf

DOI

10.1109/MTV.2007.18

Filename

4620158